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| data sheet no. pd60225 rev b irmck203 high performance sensorless motion control ic features complete sensorless control ic for permanent magnet ac motors no phase voltage feedback sensing required sinusoidal current waveform with synchronously rotating frame closed loop current control high starting torque and smooth speed ramping direct interface to ir2175 current sensing high voltage ic auto retry at startup with configurable starting torque versatile loss minimization space vector pwm serial communication interface (rs232c, rs422, spi) i 2 c serial interface to 1k bit serial eeprom for parameter storage for stand alone operation phase loss/overcurrent/overvoltage protection 7-bit discrete i/o for sequencing and status monitor integrated brake igbt control for dc bus voltage limitation servodesigner tm tool for easy operation parallel interface for microcontroller expansion product summary max clock input 33.3 mhz sensorless control computation time 10 sec max speed operating range (typical) 5% to 100% speed control resolution 15 bit full range adjustable current limit at start-up 15 bit full range programmable retry on start-up max 16 trials over current, speed, phase loss, dc bus fault protection pwm carrier frequency 16 bit/33mhz ir2175 current feedback data resolution 10bit inverter leg current sensing (optional) 12bit rs232c speed up to 57.6 kbps optional rs422 communication up to 1 mbps max spi clock 8 mhz package: qfp80 description irmck203 is a high performance digital motion control ic for sensorless ac permanent magnet motor application. control is based on closed loop vector control for sinusoidal back emf mo tors. with irmck203, the users can readily build a high performance sensorless drive system wit hout any programming effort and minimum start-up time. built-in unique start-up and ramping algorithm enables wide application. this ic is versatile enough that the users can configure and optimize system performance according to the needs of each application. with international rectif ier imotion products including high voltage ics such as ir2175 current sensing ic and iram series of intelligent igbt module in combination with irmck203, the end result is a fully optimized system with reduced electronics com ponent counts. this simplifies the design for low cost sensorles s drive modules. irmck203 can be easily adapted to various permanent magnet motors through servodesigner tm tool, which is the fully configurable graphi c user interface tool. this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. downloaded from: http:///
irmck203 overview irmck203 is a new international rectifier integrated ci rcuit device designed for one-chip solution for complete closed loop current and velo city control of a high performance sensorle ss drive for pm motors. unlike a traditional microcontroller or dsp, irmck203 does not require any programming to complete complex sensorless algorithm development. combined with international rectifier's high voltage gate drive and current sensing ic, the user can implement complete speed control of pm motors with minimum component count and virtually no design effort. in addition to sensorless closed loop speed control operation, features such as start-up retry, phase loss detection, low loss pwm, regeneration braking control and vari ous drive protections are all implemented inside irmck203. analog and digital i/os can also be configured. host communication logic contains asynchronous communication interface for rs232c or rs422 communication interface, a fast slave spi interface and an 8 bit wide host parallel interface. all communication ports have the same access capability to the host register set. the users can write to, and read from the predefined registers to configure and monitor the drive through these communication ports. irmck203 main functions ? complete closed loop current control based on synchronously rotating frame field orientation (using rotor angle observer) ? closed loop velocity control based on estimated speed ? configurable parameters (pi controller gain s, pi output limit range, current feedback scaling, pwm carrier frequency) provide adaptation to various pm motors ? built-in sensorless control logic for st art-up, ramping, and running conditions ? auto retry (programmable) on start-up with configurable torque current limit ? analog reference input (can be used for speed reference) ? rs232c/rs422 reference input ? full dynamic braking control for dc bus voltage limitation ? cycle-by-cycle on/off control for brake igbt ? loss minimization space vector pwm with deadtime insertion ? build-in two ir2175 current sensing ic interfaces ? phase loss, overcurrent (gatekill input), ov ervoltage, undervoltage, overspeed protection ? low cost serial 12bit a/d interface with multiplexer and sample/hold circuit ? optional inverter leg (low side) current sensing in lieu of ir2175 ic ? 4 channel analog output (pwm) ? local eeprom for startup initializa tion of internal data/parameter s through host register interface at24c01a, 128x8 ? versatile host communication interface rs232c or rs422 host interface fast spi slave host interf ace with multi-drop capability parallel host interface (total 12 pins) ? multiplexed data/address bus address enable rd/wr ? discrete i/os for standalone mode operation startstop (input) estop (input) this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 2 downloaded from: http:/// irmck203 dir (input) fltclr (input) fault (output) sync (output) redled (output) greenled (output) this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 3 downloaded from: http:/// irmck203 table of contents overview ........................................................................................................................................................................... 2 irmck203 main functions .............................................................................................................................................. 2 irmck203 block diagrams ............................................................................................................................................. 7 basic block diagram .................................................................................................................................................... 7 input/output of irmck203 .......................................................................................................................................... 8 application connections ............................................................................................................................... .............. 12 ic crystal clock circuitry ............................................................................................................................... ........... 13 pll clock circuitry .................................................................................................................................................... 14 low pass filter ............................................................................................................................................................ 14 implementing the low pass filter shield ............................................................................................................... 15 cp rp and cs component values ........................................................................................................................... 15 pll reset .................................................................................................................................................................... 15 dc electrical characteristic s and operating conditions ................................................................................................ 16 absolute maximum ratings ............................................................................................................................... ......... 16 recommended operating conditions ......................................................................................................................... 16 dc characteristics ...................................................................................................................................................... 17 common quiescent and leakage current .................................................................................................................. 17 input characteristics C non schmitt inputs ................................................................................................................ 17 input characteristics C schmitt inputs ........................................................................................................................ 17 output characteristics ............................................................................................................................... .................. 17 output characteristics osc2clk .............................................................................................................................. 1 8 pin and i/o characteristic table ............................................................................................................................... .. 19 power consumption .................................................................................................................................................... 21 ac electrical characteristic s and operating conditions ................................................................................................ 22 system level ac characteristics ............................................................................................................................... .22 sync pulse to sync pulse timing ............................................................................................................................ 22 fault and redled response to gatekill ................................................................................................... 23 host interface ac characteristics ............................................................................................................................... 24 spi timing .............................................................................................................................................................. 24 host parallel timing ................................................................................................................................................... 25 host parallel read cycle ............................................................................................................................... .......... 25 host parallel write cycle ............................................................................................................................... ......... 26 discrete i/o electrical characteristics ........................................................................................................................ 27 motion peripheral electrical characteristics ............................................................................................................... 28 pwm electrical characteristics .............................................................................................................................. 2 8 ir2175 interface ..................................................................................................................................................... 28 analog interface electrical characteristics ................................................................................................................. 29 adc timing ............................................................................................................................................................ 29 pll interface electrical characteristics ...................................................................................................................... 30 appendix a host register map ............................................................................................................................... .... 31 register access ........................................................................................................................................................... 31 host parallel access ............................................................................................................................... ................. 31 spi register access ............................................................................................................................... ................. 31 rs-232 register access ............................................................................................................................... ........... 31 write register definitions ............................................................................................................................... ........... 36 pwmconfig register group (write registers) ....................................................................................................... 36 currentfeedbackconfig register group (write registers) .................................................................................... 37 systemcontrol register group (write registers) ................................................................................................... 38 torqueloopconfig register group (write registers) ............................................................................................ 38 velocitycontrol register group (write registers) ................................................................................................. 39 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 4 downloaded from: http:/// irmck203 faultcontrol register group (write registers) ...................................................................................................... 40 systemconfig register group (write registers).................................................................................................... 41 eepromcontrol registers (write registers) ............................................................................................................ 42 closedloopangleestimator registers (write registers) ........................................................................................ 43 openloopangleestimator registers (write registers) .......................................................................................... 44 startupangleestimator registers (write registers) ................................................................................................ 44 startupretrial regist ers (write registers) .............................................................................................................. 45 phaselossdetect registers (write registers) ......................................................................................................... 47 d/aconverter registers (write registers) ............................................................................................................. 47 factory test register (write register) ................................................................................................................... 48 read register definitions ............................................................................................................................... ............ 49 systemstatus register group (read registers) ...................................................................................................... 49 dcbusvoltage register group (read registers) .................................................................................................... 49 focdiagnosticdata register group (read registers) ............................................................................................. 50 faultstatus register group (read registers) .......................................................................................................... 51 velocitystatus register group (read registers) .................................................................................................... 52 currentfeedbackoffset register group (read registers) ...................................................................................... 53 eepromstatus registers (read registers) ............................................................................................................... 53 focdiagnosticdatasupplement register group (read registers) ........................................................................ 54 productidentification registers (read registers) ................................................................................................... 55 factory register (read register) ............................................................................................................................ 55 appendix b package .................................................................................................................................................... 56 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 5 downloaded from: http:/// irmck203 table of figures figure 1: irmcs2031 simplified blocks ......................................................................................................................... 7 figure 2: input/output of irmck203 .............................................................................................................................. 8 figure 3: application connection of irmck203 ........................................................................................................... 12 figure 4: oscillator circuit ............................................................................................................................... .............. 13 figure 5: pll low pass filter shielding ........................................................................................................................ 14 figure 6: system level sync to sync timing .......................................................................................................... 22 figure 7: fault and redled response to gatekill ............................................................................................ 23 figure 8: spi timing....................................................................................................................................................... 24 figure 9: host parallel read cycle ............................................................................................................................... .. 25 figure 10: host parallel write cycle .............................................................................................................................. 2 6 figure 11: discrete i/o timing ............................................................................................................................... ........ 27 figure 12: pwm timing............................................................................................................................... .................. 28 figure 13: ir2175 interface ............................................................................................................................... ............. 28 figure 14: top level adc timing ............................................................................................................................... .29 table of tables table 1: typical values for the clock circuit ................................................................................................................ 13 table 2: pll test pin assignments ............................................................................................................................... .14 table 3: pll low pass filter values ............................................................................................................................. 15 table 4: absolute maximum ratings ............................................................................................................................. 16 table 5: recommended operating conditions ............................................................................................................... 16 table 6: dc characteristics ............................................................................................................................... ............. 17 table 7: non schmitt input characteristics .................................................................................................................... 17 table 8: schmitt input characteristics ............................................................................................................................ 17 table 9: output characteristics ............................................................................................................................... ........ 17 table 10: output characteristics osc2clk .................................................................................................................. 18 table 11: pin and i/o characteristics ............................................................................................................................. 21 table 12: irmck203 power consumption .................................................................................................................... 21 table 13: system level sync to sync timing ........................................................................................................... 22 table 14: fault and redled response to gatekill ........................................................................................... 23 table 15: spi timing ...................................................................................................................................................... 24 table 16: host parallel read cycle timing .................................................................................................................... 25 table 17: host parallel write cycle timing ................................................................................................................... 26 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 6 downloaded from: http:/// irmck203 irmck203 block diagrams basic block diagram figure 1 shows the basic block diagram of the irmck203 surrounded by international rectifiers ics. host communications are provided over spi, rs-232c or host parallel ports. two current sensing ics (ir2175) and a three phase high voltage gate drive typically implement th e high voltage / current interface between the irmck203 ic and motor. the irmck203 can operate in a stand-alone mode without the host controller. a serial eeprom would be utilized to load motor-specific parameters into the ic. host controller ir2175 ir2175 irmck203 motor ac power irmcs2031 rs232c or rs422 j e j e 2/3 dead time host register interface configuration registers monitoring registers spi interface space vector pwm period/duty counters period/duty counters brake fault + - - + - + a/d interface a/d mux select dc bus dynamic brake control analog speed reference dc bus feedback parallel interface ir2136 iramy20up60a plug-n-drive tm igbt module eeprom rotor angle/ speed estimator 4 channel d/a analog monitor ramp figure 1: irmcs2031 simplified blocks configurable parameters are provided to tailor design to va rious applications (motor and load). these configurable parameters can be modified via the host register in terface through the communication interface. in the irmck203 product, a design spread sheet is provided to aid the user for ease of drive start-up, th e spread sheet will input high level application data such as motor name plate informa tion, max speed, current limit, speed and current regulator bandwidth, base on this information the program will generate the required configurable parameters. detail on drive commissioning is described in the irmck203 application developers guide. all logic and algorithms are pre-programmed, and the user does not need to make any effort to develop code, alleviating the tedious design process. if needed, the user can configure the drive to tailor the control per specific this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 7 downloaded from: http:/// irmck203 needs to meet the required specification. this confi guration can be easily done by accessing the host register interface through the communication interface. input/output of irmck203 the i/o signals are shown in figure 2. the interface signals are divided into s ub-groups. for detailed pin assignment, please refer to appendix (pin definition). irmck203 tx rx baudsel startstop estop fltclr sync fault sca hpd[0-7] hpoen hpwen scl redled spiclk spimiso spimosi spicsn bypassmode pwmuh pwmul pwmvh pwmvl pwmwh pwmwl brake gatekill ifb[0-1] adclk adout adconvst admux[0-2] ressample pwm gate signal interface ir2175 interface a/d interface spi interface parallel interface discrete i/o serial eeprom led/status pll clock control greenled rs232c interface hpcsn hpa osc1clk osc2clk crystal plltest xpd chgo avdd lpvss vsshc dac[0-3] d/a interface (pwm output) resetn system reset dir fltclrout figure 2: input/output of irmck203 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 8 downloaded from: http:/// irmck203 host interface group signal input (i) / output (o) low (l) / high (h) true asserted function spiclk i positive edge sensitive spi clock spimiso o - master input and slave output spimosi i - master output and slave input spicsn i l spi chip select hp_noe i l parallel data output enable hp_nwe i l parallel data write cycle identification hp_d [7:0] i/o - parallel data hp_a i h parallel data address cycle identification hp_ncs i l chip select tx o - rs-232 data out rx i - rs-232 data in baudsel[1:0] i h rs-232 baud rate: 00 = 19.3k bps; 01 = 38.4k bps 10 = 57.6k bps; 11 = 1.031250m bps sync o l start of pwm cycle clk1xout o - 33.333 mhz output of pll. this signal has no phase relationship with the osc1clk or osc2clk inputs. discrete i/o group signal input (i) / output (o) low (l) / high (h) true asserted function startstop i h start / stop command edge sensitive dir i h forward/reverse direction command, level sensitive faultclr i h fault clear estop i h emergency stop, state sensitive pwen o h pwm enable/disable state sync o h sync pulse fault o h fault state this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 9 downloaded from: http:/// irmck203 motion peripheral group signal input (i) / output (o) low (l) / high (h) true asserted function pwmuh o pwm phase u high side pwmul o pwm phase u low side pwmvh o pwm phase v high side pwhvl o pwm phase v low side pwmwh o pwm phase w high side pwmwl o - pwm phase w low side brake o l igbt gate gatekill i varies, based on write register 0x0c bit 7 when asserted, negates all six pwm signals, host writeable ifb0 i - channel 0 (phase v) ifb1 i - channel 1 (phase w) analog interface group signal input (i) / output (o) low (l) / high (h) true asserted function adclk o negative edge sensitive clock to ads7818 adout i - serial data from ads7818 dac [3:0] o - diagnostic dac adconvst o l conversion start to ads7818 ressample o sample/hold control signal channel 0 a/d converter admux0 o h analog input mux select admux1 o h analog input mux select pll interface group signal input (i) / output (o) low (l) / high (h) true asserted function xpd i l pll reset resetn i l digital logic reset bypassclk i h internal test pin ? force to logic low bypassmode i h internal test pin ? force to logic low osc1clk i - 33.33 mhz crystal input osc2clk i - 33.33 mhz crystal input plltest i h internal test pin ? force to logic low chgo i/o - low pass filter lpvss i/o - low pass filter ground this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 10 downloaded from: http:/// irmck203 miscellaneous group signal input (i) / output (o) low (l) / high (h) true asserted function sca i/o - eeprom data scl o positive edge sensitive eeprom clock greenled o h led signal redled o h led signal power supply group signal function lvdd ic logic +3.3v power supply avdd ic phase lock loop +3.3v analog power supply mvdd ic phase lock loop +3.3v digital power supply vss ic logic power supply return vsshc ic phase lock loop power supply return this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 11 downloaded from: http:/// irmck203 application connections typical application connection is shown in figure 3. in or der to complete a sensorless drive control, all necessary components are shown in connection to irmck203. although this is a typical hardware configuration, users can customize the design without the effort of modifying code. irmck203 digital control ic tx rx estop fltclr sync fault sca hpd[0-7] hpoen,hpwen scl redled spiclk spimiso spimosi spicsn osc1clk pwmuh pwmul pwmvh pwmvl pwmwh pwmwl brake gatekill ifb0 adclk adout adconvst admux0 motor current sensing to pc optional microcontroller discrete i/o switches serial eeprom bi-color led system clock ir2175 ir2175 ads7818 4051 ifb1 admux1 popo 5v5v 33mhz crystal gate drive & igbts isolator isolator faultclr motor phase shunt motor phase shunt spi interface max232a 8051 up led at24c01a analog speed reference dc bus voltage dac0 dac1 dac2 dac3 analog output baudsel[1:0] 2-leg shunt current sensing (optional) osc2clk hpcsn,hpa greenled admux2 ressample dir startstop bypassclk bypassmode plltest chgo lpvss pll low pass filter figure 3: application connection of irmck203 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 12 downloaded from: http:/// irmck203 ic crystal clock circuitry the clock input to the ic is a 33.33 mhz crystal oscillator. two shunt capacitors and a po ssibly a series resistor is required to terminate the crystal to the ic. the values of the r/c will vary based on actual pcb attributes, and some empirical analysis may be required to get the pll to start oscillating. once oscillating, verify that the signal waveform at the osc1clk and osc2clk pins are sinusoidal rather than trapezoidal. refer to table 1 for sugge sted r/c values. most low-cost crystals can be used in this application. an example is a citizen part number cm309b33.333mabjt available from digi-key under part number 300-4160-1-nd. osc1clk osc2clk c1 irmck203 c2 r1 xtal r2 figure 4: oscillator circuit component value units xtal 33.33 mhz c1 5 pf c2 5 pf r1 0 ? r2 3.9k ? table 1: typical values for the clock circuit this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 13 downloaded from: http:/// irmck203 pll clock circuitry the irmck203 contains a pll that creates a 2x and 4x clock from the input 33.33 mhz input clock pin. there are a number of pins on the ic allocated for factory testing purposes that need to be connected to vss. table 2 shows required pcb signal connections for these pins. pin number pcb connection 1 vss 7 vss table 2: pll test pin assignments low pass filter the low pass filter for this pll resides between the chgo and lpvss pins. three passi ve components are required to implement this filter: cp, rp and cs. figure 5 shows how to place these components around the ic. a shield should be placed below rp, cp and cs made out of copper etch. chgo lpvss rp cp cs ir m c k 203 s hielded by lp v s s figure 5: pll low pass filter shielding this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 14 downloaded from: http:/// irmck203 implementing the low pass filter shield make all connections between chgo, rp, cp, cs and lpvss as short as possible. create the underlining shield by copper filling a larger area in the signal plane of the pcb. connect this shie ld to the lpvss pin of the ic. do not connect this shield to signal ground (vss). cp rp and cs component values for a typical fr4 pcb, the values of the passive components are shown in table 3. component value units rp 3.9k ? cp 1000 pf cs not installed - table 3: pll low pass filter values pll reset there are two reset pins on the ic, xpd and resetn both low true. xpd holds the pll circuitry in reset when low. upon xpd going high, the pll circuitry begins to lock onto the 33.33 mhz clock input. the pll circuit may take up to 1 msec to become stable. resetn asserted low holds the internal dsp logic in reset. upon resetn going high, the ic digital logic becomes active. reset should be held low during and at least 1 ms after xp d goes high false to hold the internal logic in reset while the pll becomes stable. this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 15 downloaded from: http:/// irmck203 dc electrical characteristics and operating conditions absolute maximum ratings note: vss = 0 volt parameter symbol limits unit s note power supply voltage vdd vss-0.3 to 4.0 v input voltage vi vss-0.3 to vdd+0.5 v non 5 volt tolerant pins (table 11) input voltage vi vss-0.3 to 7 v only on 5 volt tolerant pins (table 11) output voltage vo vss-0.3 to vdd+0.5 v output current per pin iout +/- 30 ma storage temperature tstg -65 to 150 c table 4: absolute maximum ratings recommended operating conditions note: vss = 0 volt parameter symbol min typ max units note power supply voltage vdd 3.0 3.3 3.6 v input voltage vi vss - vdd v non 5 volt tolerant pins (table 11) input voltage vi vss - 5.5 v only on 5 volt tolerant pins (table 11) ambient temperature ta -40 - 85 c note 2 table 5: recommended operating conditions notes: 2. the ambient temperature range is recommended for tj= -40 to 125 c this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 16 downloaded from: http:/// irmck203 dc characteristics common quiescent and leakage current parameter symbol conditions min typ max units quiescent current idds vi=vdd or vss vdd=max ioh=iol=0 ta=tj=85c - - .35 ua input leakage current ili vdd=max vih=vdd vil=vss -1 - 1 ua table 6: dc characteristics input characteristics ? non schmitt inputs parameter symbol conditions min typ max units high level input voltage vih1 vdd=max 2.0 - - v low level input voltage vil1 vdd=min - - 0.8 v table 7: non schmitt input characteristics input characteristics ? schmitt inputs parameter symbol conditions min typ max units high level input voltage vt1+ vdd=max 1.1 - 2.4 v low level input voltage vt1- vdd=min 0.6 - 1.8 v hysteresis voltage vh1 vdd=min 0.1 - - v table 8: schmitt input characteristics output characteristics parameter symbol conditions min typ max units high level output voltage voh3 vdd=min ioh=-12ma vdd - 0.4 - - v low level output voltage vol3 vdd=min ioh = 12ma - - vss + 0.4 v table 9: output characteristics this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 17 downloaded from: http:/// irmck203 output characteristics osc2clk parameter symbol conditions min typ max units high level output voltage lvoh vdd=min ioh=-530ua vdd - 0.4 - - v low level output voltage lvol vdd=min ioh = 730ua - - vss + 0.4 v table 10: output characteristics osc2clk this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 18 downloaded from: http:/// irmck203 pin and i/o characteristic table pin number pin name internal ic resistor termination pin type 5.50 volt tolerant input input dc characteristic table output dc characteristic table 1 bypassmode 40k-240k pull down i - table 8 - 2 fltclrout o - - table 9 3 osc1clk i - table 7 4 lvdd p - - - 5 osc2clk o - table 10 6 vss p - - - 7 plltest 20k-120k pull down i - table 7 - 8 xpd i - table 7 - 9 vsshc p - - - 10 mvdd p - - - 11 vsshc p - - - 12 avdd p - - - 13 chgo o - - - 14 lpvss p - - - 15 dir 20k ? 120k pull down i yes table 8 - 16 resetn 20k -120k pull up i - table 8 - 17 spicsn i - table 8 - 18 redled o - - table 9 19 greenled o - - table 9 20 vss p - - - 21 pwmwl o - - table 9 22 pwmwh o - - table 9 23 pwmvl o - - table 9 24 lvdd p - - - 25 pwmvh o - - table 9 26 pwmul o - - table 9 27 vss p - - - 28 pwmuh o - table 9 29 brake o - - table 9 30 baudsel0 20k ? 120k pull down i yes table 8 31 gatekill 20k -120k pull up i - table 8 - 32 ifb1 i yes table 8 - 33 ifb2 i yes table 8 - 34 lvdd p - - - 35 clk1xout o - - table 9 36 vss p - 37 spimosi i yes table 8 38 spimiso o - - table 9 39 spiclk i yes table 8 - 40 tx o - - table 9 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 19 downloaded from: http:/// irmck203 pin number pin name internal ic resistor termination pin type 5.50 volt tolerant input input dc characteristic table output dc characteristic table 41 rx i yes table 8 - 42 baudsel1 20k -120k pull up i yes table 8 - 43 lvdd p - - - 44 admux0 o - - table 9 45 vss p - - - 46 admux1 o - - table 9 47 admux2 o - - table 9 48 ressample o - - table 9 49 adconvst o - - table 9 50 adclk o - - table 9 51 adout i yes table 8 - 52 sync o - - table 9 53 fault o - - table 9 54 startstop 20k -120k pull down i yes table 8 - 55 estop 20k -120k pull down i yes table 8 - 56 fltclr 20k -120k pull down i yes table 8 - 57 lvdd p - - - 58 pwmen o - - table 9 59 dac3 o - - table 9 60 vss p - - - 61 dac2 o - - table 9 62 dac1 o - - table 9 63 dac0 o - - table 9 64 hp_d0 20k -120k pull down b - table 7 table 9 65 hp_d1 20k -120k pull down b - table 7 table 9 66 hp_d2 20k -120k pull down b - table 7 table 9 67 lvdd p - - - 68 hp_d3 20k -120k pull down b - table 7 table 9 69 hp_d4 20k -120k pull down b - table 7 table 9 70 vss p - - - 71 hp_d5 20k -120k pull down b - table 7 table 9 72 hp_d6 20k -120k pull down b - table 7 table 9 73 hp_d7 20k -120k pull down b - table 7 table 9 74 hp_noe i yes table 8 - 75 hp_nwe i yes table 8 76 hp_a i yes table 8 - 77 hp_ncs i yes table 8 - this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 20 downloaded from: http:/// irmck203 pin number pin name internal ic resistor termination pin type 5.50 volt tolerant input input dc characteristic table output dc characteristic table 78 vss p - - 79 scl o - - table 9 80 sda 20k -120k pull up b - table 7 table 9 table 11: pin and i/o characteristics power consumption parameter symbol conditions min typ max units p total ptotal vdd=3.3v - 1.2 - watt table 12: irmck203 power consumption this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 21 downloaded from: http:/// irmck203 ac electrical characteristics and operating conditions system level ac characteristics sync pulse to sync pulse timing sync angle estimation closed loop current control space vector pwm current feedback sampling t 1 t 2 t 3 t 4 t 5 figure 6: system level sync to sync timing symbol description time (sec) t 1 current feedback sample delay using ir2175 for current feedback using leg shunts for current feedback (optional) 4.3 2.0 t 2 rotor angle estimation time 4.9 t 3 current and velocity control 3.1 t 4 space vector pwm calculation time 2.3 t 5 total sync to sync minimum time 14.6 (max) table 13: system level sync to sync timing this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 22 downloaded from: http:/// irmck203 fault and redled response to gatekill gatekill fltclr redled fault t 1 t 2 t 3 t 4 t 5 figure 7: fault and redled response to gatekill symbol description min typ units t 1 fault response to gatekill 640 ns t 2 redled response to gatekill 640 ns t 3 fault response to fltclr 190 ns t 4 redled response to fltclr 190 ns t 5 gatekill pulse width 485 ns table 14: fault and redled response to gatekill this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 23 downloaded from: http:/// irmck203 host interface ac characteristics spi timing sclk mosi miso cs t sclk t css t mosis t misoz t miso figure 8: spi timing symbol description min max units f sclk spi clock frequency 8 mhz t sclk spi clock period 125 ns t css cs to sclk high setup 20 ns t mosis mosi to sclk low setup 20 ns t miso sclk to miso valid 73 ns t mioz cs to miso high impedance 15 35 ns table 15: spi timing this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 24 downloaded from: http:/// irmck203 host parallel timing host parallel read cycle hp_nwe hp_d [7:0] hp_noe hp_a hp_ncs t hpcsn valid t hpwens t hpas t hpdz t hpoen t ahpd t hpoens t hpa t hpzd figure 9: host parallel read cycle symbol description min max unit s note t hpcsn hp_ncs period 70 ns t hpwens hp_nwe setup 40 ns note 3 t hpas hp_a setup 40 ns t ahpd hp_d [7:0] access 60 105 ns t hpzd hp_d [7:0] active 0 9 ns t hpdz hp_d [7:0] high impedance 0 6 ns t hpoens hp_noe setup 40 ns note 3 t hpoen hp_noe period 70 ns table 16: host parallel read cycle timing note: 3. hp_noe, hp_nwe must be stable before the high to low transition of hp_ncs. this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 25 downloaded from: http:/// irmck203 host parallel write cycle hp_nwe hp_d [7:0] hp_noe hp_ncs t hpcsn t hpwens t hpas t hpd[7:0]s t hpoens t h p w e n t h p a t hpd[7:0] t hpoen hp_a figure 10: host parallel write cycle symbol description min max units note t hpcsn hp_ncs period 70 ns t hpwens hp_nwe setup 40 ns t hpwen hp_nwe period 70 ns t hpas hp_a setup -10 ns t hpa hp_a period 70 ns t hpd[7:0] hp_d [7:0] setup -10 ns t hpoens hp_noe setup 40 ns t hpoen hp_noe period 70 ns note 4 table 17: host parallel write cycle timing note: 4. hp_noe must be asserted high while hp_ncs low during a host parallel write cycle. this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 26 downloaded from: http:/// irmck203 discrete i/o electrical characteristics start/stop fltclr t l figure 11: discrete i/o timing symbol description min max units t l pulse width startstop 100 ns pulse width fltclr 1 us table 15: discrete i/o timing this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 27 downloaded from: http:/// irmck203 motion peripheral electrical characteristics pwm electrical characteristics sync pwmuh pwmul pwmvh pwmvl pwmwh pwmwl t deadtimeresolution t deadtimeresolution figure 12: pwm timing symbol description units t deadtimeresolution deadtime insertion logic resolution 30 ns table 16: pwm timing ir2175 interface ifb0 ifb1 t ifb t ifbl t ifbh figure 13: ir2175 interface symbol description min max units f ifb current feedback input frequency 95 165 khz t ifb current feedback period 10.52 6.06 us t ibh current feedback high pulse width 500 ns 10 us t ifbh current feedback low pulse width 500 ns 10 us table 17: ir2175 interface this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 28 downloaded from: http:/// analog interface electrical characteristics adc timing system level timing the irmck203 contains logic to drive an adc converter, analog mux and associated sample and hold circuits. figure 14 shows the system level timing of these elements. the irmck203 is specifically designed to in terface to the burr-brown ads7818 adc . as such, all interface sign als between the adc and irmck203 are guaranteed to meet worst case timing specificati ons over the irmck203 and ads7818 specified operation environment. for interfacing to other adcs, please contact international rectifier for detailed sp ecifications. also refer to the application developers guide for a detailed description of adc, mux and sample and hold signal system level protocol. adconvst ressample admux1 adclk t adclk admux0 t mux[2:0] admux2 t clkdly t 1 t 2 t 3 figure 14: top level adc timing symbol description typ units t mux[2:0] adconvst to mux[2:0] 22 ns t 1 adconvst low period 1.44 us t 2 adconvst high period 630 ns t 3 adconvst to adclk falling 60 ns t adclk adclk period 127.5 ns t clkdly adclk stall period 210 ns table 18: top level adc timing this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. downloaded from: http:/// pll interface electrical characteristics parameter symbol conditions min typ max units current consumption idds static - - 170 ua current consumption idd dynamic - 5 - ma peak jitter tpj - - - 1000 ps cycle jitter tcj - -500 - +500 ps lock-up time tlock - - - 1 ms pll reset period trst recommended operating condition 10 - - ns table 20: pll electrical characteristics this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. downloaded from: http:/// irmck203 appendix a host register map register access a host computer controls the irmck203 using its slave-mode full-duplex spi port, a standard rs-232 port or a 8-bit parallel port for connection to a micropro cessor. all interfaces are always ac tive and can be used interchangeably, although not simultaneously. control/status registers are mappe d into a 128-byte address space. host parallel access the irmck203 contains an address register that is updated with the host register address when hp_a = 1. after each subsequent data byte is either read or written, the internal address regist er is incremented. the diagram below shows that data bytes 0 to n would acce ss register locations initially specified by the address byte. the address byte with the hp_a signal can be asserted at any time. address byte hp_a = 1 data byte 0 hp_a = 0 ?????. hp_a = 0 data byte n hp_a = 0 host parallel data transfer format spi register access when configured as an spi device read only and read/wr ite operations are performed using the following transfer format: command byte data byte 0 ?????. data byte n data transfer format bit position 7 6 5 4 3 2 1 0 read only register map starting address command byte format data transfers begin at the address specified in the command byte and pro ceed sequentially until the spi transfer completes. as in the host parallel a ccess, the internal address register is incremented after each spi byte is transferred. note that accesses are read/w rite unless the read only bit is set. rs-232 register access the irmck203 includes an rs-232 interface channel that provides a direct conn ection to the host pc. the software interface combines a basic "register map" control met hod with a simple communicati on protocol to accommodate potential communication errors. this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 31 downloaded from: http:/// irmck203 rs-232 register write access a register write operation consists of a command/address by te, byte count, register data and checksum. when the irmck203 receives the register data, it validates the ch ecksum, writes the register data, and transmits and acknowledgement to the host. command / address byte byte count 1-6 bytes of register data checksum register write operation command acknowledgement byte checksum register write acknowledgement bit position 7 6 5 4 3 2 1 0 1=read/ 0=write register map starting address command/address byte format bit position 7 6 5 4 3 2 1 0 1=error/ 0=ok register map starting address command acknowledgement byte format the following example shows a command sequence sent from the host to the irmck203 requesting a two-byte register write operation: 0x2f write operation beginning at offset 0x2f 0x02 byte count of register data is 2 0x00 data byte 1 0x04 data byte 2 0x35 checksum (sum of preceding bytes, overflow discarded) a good reply from the irmck203 would appear as follows: 0x2f write completed ok at offset 0x2f 0x2f checksum an error reply to the command would have the following format: 0xaf write at offset 0x2f completed in error 0xaf checksum this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 32 downloaded from: http:/// irmck203 rs-232 register read access a register read operation consists of a command/address byte, byte count and checksum. when the irmck203 receives the command, it validates the checksum and transmits the register data to the host. command / address byte byte count checksum register read operation command acknowledgement byte register data (byte count bytes) checksum register read acknowledgement (transfer ok) command acknowledgement byte checksum register read acknowledgement (error) the following example shows a command sequence sent from the host to the irmck203 requesting four bytes of read register data: 0xa0 read operation beginning at offset 0x20 (high-order bit selects read operation) 0x04 requested data byte count is 4 0xa4 checksum a good reply from the irmck203 might appear as follows: 0x20 read completed ok at offset 0x20 0x11 data byte 1 0x22 data byte 2 0x33 data byte 3 0x44 data byte 4 0xca checksum an error reply to the command would have the following format: 0xa0 read at offset 0x20 completed in error 0xa0 checksum rs-232 timeout the irmck203 receiver includes a timer th at automatically terminates transfer s from the host to the irmck203 after a period of 32 msec. rs-232 transfer examples the following example shows a normal exch ange executing a register write access. this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 33 downloaded from: http:/// irmck203 the example below shows a normal register read access exchange. the following example shows a register write request that is repeated by the host due to a negative acknowledgement from the irmck203. in the final example, the host repeats a register read access request when it r eceives no response to its first attempt. this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 34 downloaded from: http:/// irmck203 this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 35 downloaded from: http:/// irmck203 write register definitions pwmconfig register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0xc gatekill sns (w) spare gate snsl (w) gate snsu (w) syncsns brakesns sd (w) spare 0xd pwmperiod (lsbs) (w) 0xe twophs pwm (w) twophs type (w) pwmconfig (w) pwmperiod (msbs) (w) 0xf pwmdeadtm (w) 0x44 modscl (lsbs) (w) 0x45 modscl (msbs) (w) 0x51 pwmguardband (w) pwmconfig write register map field name access (r/w) field description sd w shutdown control output to ir2137. brakesns w logic sense for brake signal out put to gate driver ic. 0 = active low, 1 = active high. syncsns w logic sense for pwm sync si gnal output to microprocessor. 0 = active low, 1 = active high. gatesnsu w upper igbt gate sense. 1 = active high gate control, 0 = active low gate control. gatesnsl w lower igbt gate sense. 1 = active high gate control, 0 = active low gate control. gatekillsns w gatekill signal sense. 1 = active high gatekill, 0 = active low gatekill. pwmperiod w pwm carrier period. actual pwm carrier period is 2 * (pwmperiod + 1) * (system clock period). pwmconfig w pwm configuration. 0 = asymmetrical center aligned pwm, 1 = symmetrical center aligned pwm. twophstype w used only for two-phase pwm modulation mode: 0 = type 1 2-phase pwm 1 = type 2 2-phase pwm twophspwm w selects pwm modulation mode: 0 = enable 3-phase space vector pwm modulation 1 = enable 2-phase space vector pwm modulation this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 36 downloaded from: http:/// irmck203 field name access (r/w) field description pwmdeadtm w gate drive dead time in units of system clock cycles (e.g., 30 ns with 33 mhz clock). modscl w space vector modulator scale fa ctor. this register, which depends on the pwm carrier frequency, should be set as follows: modscl = pwmperiod * sqrt(3) * 4096 / 2355 where pwmperiod is the value in the pwmconfig write register group?s pwmperiod register. pwmguardband w this parameter provides a guard band (scaling: 1 = 30nsec) such that pwm switching will not mi grate into the current feedback sampling instant (sync pulse region). this guard band is provided to improve feedback noise. the parameter only applies to the 3- phase space vector modulation scheme. please do not modify this parameter without consulting a motor drive fae. pwmconfig write register field definitions currentfeedbackconfig register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x15 ifbkscl (lsb) (w) 0x16 ifbkscl (msb) (w) 0x7d offsetcaldelay (w) currentfeedbackconfig write register map field name access (r/w) field description ifbkscl w rotating frame iq component and id component current feedback scale factor. constant used to scale current measurements before they are used in the field orientation calculation. this is a 15-bit fixed- point signed number with 10 fractional bits that ranges from ?16 to + 16 + 1023 / 1024. offsetcal delay w this parameter specifies the delay ti me (1 = 1 sec) to restart current offset measurement after a stop command is issued. only applies if leg shunt current feedback is selected.12-bit signed value for v phase current feedback offset. when the ifboffsenb bit in the systemcontrol write register group is "0" this value is automatically added to each current measurement in hardware. currentfeedbackconfig write register field definitions this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 37 downloaded from: http:/// irmck203 systemcontrol register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x17 spare hostestop startcmd rotation systemcontrol write register map field name access (r/w) field description rotation w direction of motor rotation: 0 = reverse motor rotation; 1 = forward motor rotation. startcmd w start/stop bit. setting this bi t to 1 issues a start command. setting this bit to 0 stops the motor. hostestop w emergency coast stop will take place when this bit is set to one. systemcontrol write register field definitions torqueloopconfig register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x1a kpireg ? current loop proportional gain (lsbs) (w) 0x1b kpireg ? current loop proportional gain (msbs) (w) 0x1c kxireg ? current loop integral gain (lsbs) (w) 0x1d kxireg ? current loop integral gain (msbs) (w) 0x22 vqlim ? quadrature current output limit (lsbs) (w) 0x23 vqlim ? quadrature current output limit (msbs) (w) 0x26 vdlim ? direct current output limit (lsbs) (w) 0x27 vdlim ? direct current output limit (msbs) (w) torqueloopconfig write register map this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 38 downloaded from: http:/// irmck203 field name access (r/w) field description kpireg w 15-bit signed current loop pi controller proportional gain. scaled with 14 fractional bits for an effective range of 0 ? 1. kxireg w 15-bit signed current loop pi cont roller integral gain. scaled with 19 fractional bits for an effective range of 0 - .03125. vqlim w 16-bit quadrature current pi controller voltage output limit. vdlim w 16-bit direct current pi controller voltage output limit. torqueloopconfig write register field definitions velocitycontrol register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x32 kpsreg ? velocity loop proportional gain (lsbs) (w) 0x33 kpsreg ? velocity loop proportional gain (msbs) (w) 0x34 kxsreg ? velocity loop integral gain (lsbs) (w) 0x35 kxsreg ? velocity loop integral gain (msbs) (w) 0x36 motorlim ? velocity loop output positive limit (lsbs) (w) 0x37 motorlim ? velocity loop output positive limit (msbs) (w) 0x38 regenlim ? ? velocity loop output negative limit (lsbs) 0x39 regenlim ? ? velocity loop output negative limit (msbs) 0x3a spdscl ? speed scale factor (lsbs) 0x3b spdscl ? speed scale factor (msbs) 0x3c targetspd ? setpoint/target speed (lsbs) 0x3d targetspd ? setpoint/target speed (msbs) 0x3e accelrate 0x3f decelrate 0x7a minspd this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 39 downloaded from: http:/// irmck203 byte offset bit position 7 6 5 4 3 2 1 0 0x18 startlim (lsbs) 0x19 startlim (msbs) velocitycontrol write register map field name access (r/w) field description kpsreg w 15-bit velocity loop proportional gain, in fixed point with 5 fractional bits. range = 0 - 512. kxsreg w 15-bit velocity loop integral gain, in fixed point with 13 fractional bits. range = 0 - 2. motorlim w motoring torque current limit (4095 = rated motor current).16-bit speed pi controller output positive limit. regenlim w regeneration torque current limit (4095 = rated motor current)16-bit speed pi controller output negativ e limit (2?s complement).. spdscl w motor speed scale factor. targetspd w velocity loop speed setpoi nt in speed units, which are determined by the user via the spdscl register setting. accelrate w acceleration rate limit. decelrate w deceleration rate limit. minspd w minimum speed protection. th is parameter sets the minimum reference speed. startlim w drive start-up current limit. (4095 = rated motor current). velocitycontrol write register field definitions faultcontrol register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x42 spare fltclr dcbusm enb faultcontrol write register map this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 40 downloaded from: http:/// irmck203 field name access (r/w) field description dcbusmenb w dc bus monitor enable. 1 = monitor dc bus voltage and generate appropriate brake signal control and disable pwm output when voltage fault conditions occur. gatekillflt and ovrspdflt faults cannot be disabled. dc bus voltage thresholds are as follows: overvoltage ? 410v brake on ? 380v brake off ? 360v nominal ? 310v undervoltage off ? 140v undervoltage ? 120v fltclr w this bit clears all active fault c onditions. the user should monitor the faultstatus read register group to determine fault status and set this bit to ?1? to clear any faults that have occurred. a fault condition automatically clears the pwmenbw and focenbw bits in the systemcontrol write register group. no te that this bit also directly controls the output 2137 fltclr pin. after clearing a fault, the user must explicitly set this bit to ?0? to re-enable fault processing. faultcontrol write register field definitions systemconfig register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x50 extctrl adcifbenb ramp stop spare systemconfig write register map field name access (r/w) field description rampstop w selects the stopping mode: 0 - configure for coast stopping 1 - configure for ramp stopping adcifbenb w selects the current feedback mode: 0 - selects ir2175 current feedback 1 - selects leg-shunt current feedback extctrl w setting this bit to ?1? enables direct control of basic motor operation via the external user interface pi ns. when this bit is ?1?, the focenbw and pwmenbw bits in the systemcontrol write register group are ignored. systemconfig write register field definitions this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 41 downloaded from: http:/// irmck203 eepromcontrol registers (write registers) at power up, the write registers can be optionally initialized with values stored in eeprom. the eepromcontrol write register group and eepromstatus read register group are used to read and write these eeprom values. since the eeaddrw write register (which selects the eeprom offset to read or write) does not require initialization at power up, the location corresponding to that register in eeprom (at offset 0x5d) is used to store a register map version code. at power on, the ir mck203 initializes the write registers from eeprom only if the version code stored at this offset in eeprom matches its internal register map version code (which can be read from the regmapver field of the eepromstatus read register group). to enable write register initialization at power up, write the appropriate register map version code to eeprom at offset 0x5d. to disable write register initialization at power up, write a zer o (or any non-matching version code) to offset 0x5d of the eeprom. byte offset bit position 7 6 5 4 3 2 1 0 0x5c spare eewrite eeread eerst 0x5d eeaddrw / regmapverscode (w) 0x5e eedataw (w) eepromcontrol write register map field name access (r/w) field description eerst w self-clearing eeprom reset. writing a "1" to this bit resets the i2c eeprom interface. eeread w self-clearing i2c eeprom read. writing a "1" to this bit initiates an eeprom read from the byte located at eeprom address eeaddrw. after setting this bit the user should poll the eebusy bit in the eepromstatus read register group to determine when the read completes and then read the data from eedatar in the eepromstatus read register group. eewrite w self-clearing eeprom write. writing a "1" to this bit initiates an eeprom write from the data byte in eedataw to the eeprom address eeaddrw . eeaddrw w eeprom address register. contains the address for the next eeprom read or write operation. eedataw w eeprom data register. contains the data for the next eeprom write operation. eepromcontrol write register field definitions this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 42 downloaded from: http:/// irmck203 closedloopangleestimator regist ers (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x60 iscl (lsbs) (w) 0x61 iscl (msbs (w) 0x62 flxbinit (lsbs) (w) 0x63 flxbinit (msbs) (w) 0x6a pllkp (lsbs) (w) 0x6b spare pllkp (msbs (w) 0x6c pllki (lsbs) (w) 0x6d spare pllki (msbs (w) 0x6e voltscl (lsbs) (w) 0x6f voltscl (msbs (w) 0x70 rs (lsbs) (w) 0x71 rs (msbs (w) 0x72 ld (lsbs) (w) 0x73 ld (msbs (w) 0x74 atantau (lsbs) (w) 0x75 atantau (msbs (w) 0x76 flxtau (lsbs) (w) 0x77 spare flxtau (msbs) (w) closedloopangleestimator write register map this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 43 downloaded from: http:/// irmck203 field name access (r/w) field description iscl w current scaler for motor flux calculation. flxbinit w initialization value of beta flux at start. pllkp w flux phase lock loop proportional gain. pllki w flux phase lock loop integral gain. voltscl w voltage scaler for motor flux calculation. rs w motor per phase resistance including cable (@25c). ld w motor per phase inductance. atantau w rotor angle estimator phase compensation gain. flxtau w rotor angle estimator flux model time constant. closedloopangleestimator write register field definitions openloopangleestimator regist ers (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x66 ktorque (lsbs) (w) 0x67 ktorque (msbs (w) 0x5f vfgain (w) openloopangleestimator write register map field name access (r/w) field description ktorque w motor mechanical model torque constant. vfgain w open-loop volts/hz flux gain. (for diagnostic use only). openloopangleestimator write re gister field definitions startupangleestimator regi sters (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x64 parki (w) 0x65 spare zero spdflt disable use2xfrq scale phslosflt disable diagnosticctrl (w) 0x68 wethr (lsbs) (w) this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 44 downloaded from: http:/// irmck203 byte offset bit position 7 6 5 4 3 2 1 0 0x69 wethr (msbs (w) 0x78 parktm (w) startupangleestimator write register map field name access (r/w) field description parki w dc current injection level during motor parking (start-up mode). diagnosticctrl w 1 (0001) ? enable parking diagnostic 2 (0010) ? enable start-up diagnostic 5 (0101) ? enable current regulator diagnostic 9 (1001) ? enable volts hertz diagnostic phslosflt disable w enable/disable phase loss fault: 0 = enable phase loss fault; 1 = disable phase loss fault use2xfrqscale w selects speed scaling: 0 - norminal speed scale 1 - reduce speed feedback scaling by half please do not modify this parameter without consulting motor control faes zerospdflt disable w zero speed fault enable/disable: 0 - enbale zero speed fault 1 - disable zero speed fault wethr w frequency threshold level (swi tch over from open-loop to closed- loop mode). parktm w time duration of parking mode. 255 = 4 sec startupangleestimator write register field definitions startupretrial register s (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x1e retrytm (lsbs) 0x1f retrytm (msbs) 0x79 parktmret 0x7b flxthrl 0x7c flxthrh this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 45 downloaded from: http:/// irmck203 byte offset bit position 7 6 5 4 3 2 1 0 0x7e numretries 0x7f parkiret startupretrial write register map field name access (r/w) field description retrytm w this parameter provides the adjus tment to the sampling instant for determination of start failure. the sampling instant starts when closed_loop = 1. scaling 1 count = 1.966 msec. please do not modify this parameter without consulting a motor drive fae. parktmret w during motor start-up, dc current is injected to the motor for maximization of startup torque per ampere rating. parktm controls the duration of dc current injection. however, users are able to use a longer duration after two or more re starts by setting this parameter (parktmret scaling 255 = 4 secs.). this is done to increase the chance of a successful start-up.start-up failure may be caused by increased shaft friction. after first start-up retry, the parking time can be increased to improve parking performance. flxthrl w the low flux threshold leve l for determining a successful startup (scaling: 129 = 100% flux). please do not modify this parameter without consulting a motor drive fae.the low flux threshold level for determining a successful startup. flxthrh w the upper flux threshold leve l for determining a successful startup (scaling: 64 = 100% flux). please do not modify this parameter without consulting a motor drive fae.the high flux threshold level for determining start-up failure. numretries w if start-up fails, the user can program start-up retrial. this parameter determines the number of start-up retr ies. a value of zero will disable startup retrial. the maximum number of retries is 15. parkiret w during motor start-up, dc current is injected to the motor for maximization of startup torque per ampere rating. users are able to use a higher level of dc current injection (parkiret scaling 255 = motor rated amp * 0.866) after two or more restarts. this is done to increase the chance of a successful start-up.start-up failure may be caused by increased shaft friction. after first start-up retry, the parking current can be increased to improve parking performance. startupretrial write register field definitions this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 46 downloaded from: http:/// irmck203 phaselossdetect registers (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x79 parktmret 0x28 adjpark1 0x29 adjpark2 0x2a retrytm phaselossdetect write register map field name access (r/w) field description adjpark1 w anticipated w-phase motor current gain scaler used during initial stage of phase loss detection. adjpark2 w anticipated w-phase motor current gain scaler used during final stage of phase loss detection. phslosthr w phase loss detection current error threshold. phaselossdetect write register field definitions d/aconverter registers (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x4f dacsel d/aconverter write register map this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 47 downloaded from: http:/// irmck203 field name access (r/w) field description dacsel w selects d/a converte r diagnostic outputs 0 - 3. a value of 0 selects: data 0 = alpha fluxflux data 1 = electrical rotor angle data 2 = alpha voltagetorque current data 3 = closed loop/open loop status (0 = open, 1 = closed) a value of 1 selects: data 0 = alpha currentdc bus voltage data 1 = torque current feedbackalpha voltage data 2 = iq reftorque current reference data 3 = motor speed a value of 2 selects: data 0 = q-axis command voltage data 1 = d-axis command voltage data 2 = alpha current data 3 = beta current a value of 3 selects: data 0 = flux magnitude data 1 = current error at parking data 2 = parking diagnostic flag data 3 = w-phase current d/aconverter write register field definitions factory test register (write register) byte offset bit position 7 6 5 4 3 2 1 0 0x58 test factory write register map field name access (r/w) field description test w reserved for factory use. data written to this register could be read from a read register at location 0x58. factory write register field definitions this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 48 downloaded from: http:/// irmck203 read register definitions systemstatus register group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x7 startstop fwdrev estop pwrid extctrlr foc enbr pwm enbr systemstatus read register map field name access (r/w) field description pwmenbr r pwm enable bit status. focenbr r foc enable bit status. extctrlr r reflects the status of the extc trl bit in the system configuration write register (address 0x50). pwrid r power id. 0 = 3 kw, 1 = 2 kw, 2 = 500 w. estop r user interface emergency stop signal (1 ? emergency stop) fwdrev r user interface ?d ir" digital input status. 1 - forward rotation request 0 - reverse rotation request startstop r user interface ?sta rt/stop" digital input status. 1 - start 0 - stop systemstatus read register field definitions dcbusvoltage register group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0xa dcbusvolts (lsbs) 0xb spare brake dcbusvolts (msbs) dcbusvoltage read register map this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 49 downloaded from: http:/// irmck203 field name access (r/w) field description dcbusvolts r dc bus voltage. data range is 0 - 4095, which corresponds to a dc bus voltage between 0 and 500 volts. brake r brake signal status. 1 = brake signal active. dcbusvoltage read regi ster field definitions focdiagnosticdata register group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0xc rotatorangle (lsb) 0xd spare parking done start_ fail closed_ loop rotatorangle (msb) 0xe id ? synchronous frame direct current (lsbs) 0xf id ? synchronous frame direct current (msbs) 0x10 iq ? synchronous frame quadrature current (lsbs) 0x11 iq ? synchronous frame quadrature current (msbs) 0x12 iqref_c ? synchronous frame quadrature current command (lsb) 0x13 iqref_c ? synchronous frame quadrature current command (msb) 0x14 flx_alpha ? estimated motor flux (lsb) 0x15 flx_alpha ? estimated motor flux (msb) 0x16 i_alpha ? alpha frame current (lsb) 0x17 i_alpha ? alpha frame current (msb) 0x18 v_alpha ? alpha frame voltage (lsb) 0x19 v_alpha ? alpha frame voltage (msb) focdiagnosticdata read register map this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 50 downloaded from: http:/// irmck203 field name access (r/w) field description rotatoranlge r estimated rotor angle (electrical), which is used for synchronous frame to stationary frame transformation. the scaling is 4096 = 2pi. the range is 0 ? 4095. closed_loop r this is a drive control status flag which indicates that the drive has switched from open-loop to closed-loop operation. the switch over is done during drive start-up (initial speed ramping) start_fail r this is a drive control status flag i ndicating that the drive has failed to start due to various reasons (for in stance: shaft jam). the start-stop sequencer uses this bit and param eter numretry to determine whether a start-up retry should be activated. parking done r this is a status flag indicating that the drive has finished obtaining the initial rotor angle (parking) for motor startup. during drive start-up, the first start-up stage is parking stage. id, iq r synchronous or rotating frame dire ct and quadrature current values in 2?s complement representation. the full scale current values range from ?16384 to 16383. (scaling: 4095 = rated motor current) iqref_c r synchronous or rotating frame quadr ature current command values in 2?s complement representation. the full scale current values range from ?16384 to 16383. flx_alpha r estimated motor flux value. scaling is 5000 = rated motor flux. i_alpha r stationary frame current. scali ng is platform dependent (current shunt resistor). drive commissi oning tool (spreadsheet) provides the scaling of i_alpha (aibi scale). v_alpha r stationary frame alpha voltage. this voltage is constructed by dc bus voltage and modulation index in the stationary frame. the scaling is platform dependent. focdiagnosticdata read regi ster field definitions faultstatus register group (read registers) the fault status register records fault conditions that occur during drive operation. when any of these fault conditions occur, the pwm output is automatically disabled. the user should monitor this register continuously for fault conditions. a fault condition can be cleared by writing a 1 to the faultclr bit in the faultcontrol write register group. (this does not automatically re-enable pwm output.) byte offset bit position 7 6 5 4 3 2 1 0 0x1e phsloss flt retryflt zerospd flt exectm flt ovrspdflt ovflt lvflt gatekillflt faultstatus read register map field name access (r/w) field description gatekillflt r filtered and latched version of ir2137 fault output. lvflt r dc bus low voltage fault. this fault occurs if the dc bus drops below 120v. this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 51 downloaded from: http:/// irmck203 field name access (r/w) field description ovflt r dc bus overvoltage fault. this fault occurs if the dc bus voltage exceeds 410v. ovrspdflt r over speed fault. this fault occu rs whenever the motor reaches the positive or negative limits. the user should use the scale factor in the spdscl field of the velocityc ontrol write register group to scale the motor speed so that it falls between -16384 and +16383 with these limits as the over speed condition. exectmflt r execution time fault. zerospdflt r zero speed fault. when speed is less than minspd/2 (half minimum speed) for a continuous period of 4 seconds, the zero speed fault will be set. retryflt r start-up retry fault. after a certain number (determined by parameter numretries) of start-up failures, this fault will be set. phslossflt r phase loss fault. drive to motor phase connection may be loose. faultstatus read regist er field definitions velocitystatus register group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x26 spd (lsbs) 0x27 spd (msbs) velocitystatus read register map field name access (r/w) field description spd r current motor speed in speed units. (see the description of spdscl in the velocitycontrol write register group.) velocitystatus read register field definitions this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 52 downloaded from: http:/// irmck203 currentfeedbackoffset register group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x30 ifbvoffs (lsbs) (r) 0x31 ifbwoffs (lsbs) (r) ifbvoffs (msbs) (r) 0x32 ifbwoffs (msbs) (r) currentfeedbackoffset read register map field name access (r/w) field description ifbvoffs, ifbwoffs r current feedback offset values from t he last ifb offset calculation. these values are automatically applied to each current feedback measurement value whenever the ifboffsenb bit in the systemcontrol write register group is set. currentfeedbackoffset read register field definitions eepromstatus registers (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x38 spare eebusy 0x39 eddatar (r) 0x3a eeaddrr (r) eepromstatus read register map field name access (r/w) field description eebusy r i2c eeprom interface busy bit. t he user should wait for this bit to clear before initiating eeprom read or write operations. this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 53 downloaded from: http:/// irmck203 field name access (r/w) field description eedatar r eeprom data register. contains the data from the last eeprom read operation. note that writing to the eerst field in the eepromcontrol write register gr oup invalidates this register. eeaddrr r eeprom address read register shows the value stored in eeprom at the offset of the eeaddrw writ e register (0x5d). since this address in the eeprom contains the bpirmck203 register map version, the user can read this fi eld to determine whether or not the write registers were initialized at power on. eepromstatus read register field definitions focdiagnosticdatasupplement regi ster group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x3c elecangr (lsbs) (r) 0x3d spare elecangr (msbs) (r) 0x3e spdref (lsbs) (r) 0x3f spdref (msbs) (r) 0x40 spderr (lsbs) (r) 0x41 spderr (msbs) (r) 0x42 iqrefr (lsbs) (r) 0x43 iqrefr (msbs) (r) focdiagnosticdatasupplement read register map field name access (r/w) field description elecangr r electrical angle. spdref r speed pi controller reference input. spderr r speed pi controller error. iqrefr r speed pi controller output. focdiagnosticdatasupplement read register field definitions this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 54 downloaded from: http:/// irmck203 productidentification regi sters (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x7c productid (r) 0x7d regmapverid (r) 0x7e revcodeid (lsbs) (r) 0x7f revcodeid (msbs) (r) productidentification read register map field name access (r/w) field description productid r product identification code. regmapverid r current register map version code. revcodeid r irmck203 revision code. revi sion code format is ?xx.xx?, where each ?x? is a 4-bit hexadecimal number. productidentification read re gister field definitions factory register (read register) byte offset bit position 7 6 5 4 3 2 1 0 0x58 test (r) factory read register map field name access (r/w) field description test r data value resulting from a wr ite to write register 0x58. used for factory use only. factory read register field definitions this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 55 downloaded from: http:/// irmck203 appendix b package this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 56 downloaded from: http:/// irmck203 this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 57 ir world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 252-7105 http://www.irf.com data and specifications subject to change without notice. 9/15/2003 sales offices, agents and distributors in major cities throughout the world. downloaded from: http:/// |
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